1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly to a method of manufacturing a semiconductor device, a nonvolatile semiconductor memory device and a method of manufacturing the same, wherein a buried diffusion layer serves as a signal line.
2. Description of the Related Art
Semiconductor memory devices known as typical semiconductor devices are classified into two types: volatile memories; and, nonvolatile memories. Of these memories, whereas the volatile ones lose their stored data when their power source is turned off, the nonvolatile ones may keep their stored data even when their power source is turned off. The former or volatile memories are known as RAMs (i.e., Random Access Memories), and the latter or nonvolatile memories are known as ROMs (i.e., Read Only Memories).
Of the above-mentioned semiconductor devices, particularly the ROMs are used in various types of information processing apparatuses. Of these ROMs, EPROMs (i.e., Erasable and Programmable ROMs)xe2x80x9d and EEP (i.e., Electrically Erasable and Programmable ROMs) are widely known. In the EPROMs, their stored information may be erased by applying ultraviolet rays thereto, and also may be electrically stored therein again. On the other hand, in the EEPs, their stored information may be electrically erased and stored therein again. Further, of the EEPROMS, ones capable of performing information""s block erasing and byte writing operations are known as flash memories, which are noted for their abilities to replace the floppy disks and the hard disks both typical of conventional memory means.
Any one of such writable and nonvolatile semiconductor memory devices has an MIS (i.e., Metal Insulator Semiconductor) type construction, in which a metallic gate has a laminated construction and is therefore constructed of: a floating gate buried in an insulation film; and, a control gate formed over this floating gate through the insulation film. In operation, information is stored in a memory cell of the nonvolatile semiconductor memory device by injecting an electric charge into the floating gate of the memory cell which is electrically isolated from the other memory cells in the semiconductor memory device, wherein the floating gate may keep the electric charge thus injected therein even when its power source is turned off.
In such a conventional type of nonvolatile semiconductor memory device and a method of manufacturing the same as those disclosed in Japanese Patent Laid-Open No. Hei 6-283721, for example: buried diffusion layers are formed in a semiconductor region so as to be disposed adjacent to opposite end portions of the floating gate described above, so that the buried diffusion layers are used as bit lines of the semiconductor memory device. FIG. 30 shows a plan view of the above-mentioned conventional type of nonvolatile semiconductor memory device. FIG. 31 shows a cross-sectional view of the conventional nonvolatile semiconductor memory device, taken along the line Axe2x80x94A of FIG. 30. As shown in FIGS. 30 and 31, for example, in an active region defined by a device isolation region or oxide film 52 formed in a P-type semiconductor substrate 51, a first floating gate 54 and a second floating gate 55 are formed side by side and insulated from each other through a gate oxide film 53. Formed in the P-type semiconductor substrate 51 so as to be disposed adjacent to outer end portions of both the first floating gate 54 and the second floating gate 55 are N-type drain regions 56, 57. Further, formed in the P-type semiconductor substrate 51 so as to be disposed between the first floating gate 54 and the second floating gate 55 is an N-type source region 58. A first memory transistor is constructed of the first floating gate 54, N-type drain region 56 and the N-type source region 58. On the other hand, a second memory transistor is constructed of the second floating gate 55, N-type drain region 57 and the N-type source region 58. As is clear from the above, the N-type source region 58 is used in both the first and the second memory transistor.
The first floating gate 54 and the second floating gate 55 are covered with an insulation film 60, which is a so-called xe2x80x9cONO (i.e., Oxide-Nitride-Oxide)xe2x80x9d laminated film constructed of, for example, a silicon oxide film, silicon nitride film and a silicon oxide film. Formed over both the first floating gate 54 and the second floating gate 55 through this insulation film 60 is a control gate 61. In general, each of the first floating gate 54, second floating gate 55 and the control gate 61 is made of polysilicon.
In the above-mentioned construction of the nonvolatile semiconductor memory device, as shown in FIG. 30, each of these regions 56, 57 and 58 is constructed of a buried diffusion layer, and serves as a bit line covering a plurality of memory cells of the semiconductor memory device, wherein the memory cells are disposed adjacent to each other. On the other hand, as is clear from FIG. 30, the control gate 61 extends in a direction substantially perpendicular to a longitudinal direction of each of these bit lines 56, 57 and 58 to serve as a word line. Next, with reference to each of FIGS. 32A, 32B, 32C, 33A and 33B, a method of manufacturing the conventional nonvolatile semiconductor memory device will be described in the order of its processing steps.
First, as shown in FIG. 32A, an oxidation-resistant mask film 63 constructed of a silicon nitride film is formed in an active region of a P-type semiconductor substrate 51 through a buffer film 62 of silicon oxide, and then subjected to an oxidation process which is well known as a so-called xe2x80x9cLOCOS (i.e., Local Oxidation Silicon) processxe2x80x9d, so that a device isolation oxide film 52 serving as a field oxide film is formed.
Then, both the buffer film 62 and the oxidation-resistant mask film 63 are removed. After that, as shown in FIG. 32B, a gate oxide film 53 is formed to cover the active region through a normal oxidation process. Then, by using a CVD (i.e., Chemical Vapor Deposition) process, a first conductive layer 64 made of polysilicon is formed on the entire surface of the semiconductor substrate 51. Here, it will be understood that when a layer or film is referred to as being formed xe2x80x9conxe2x80x9d another film or substrate, it can be directly on such another film or substrate, or intervening films may also be present therebetween. Subsequent to the above CVD process, as shown in FIG. 32C, a resist film 65 is formed by using a photolithography process to cover a region in which a floating gate for the first conductive layer 64 should be formed. Under such circumstances, the first conductive layer 64 is subjected to a patterning process, so that the first floating gate 54 and the second floating gate 55 both constructed of the first conductive layer 64 are formed side by side and spaced apart from each other to extend in the same direction. In forming both the first floating gate 54 and the second floating gate 55 through the above-mentioned patterning process of the first conductive layer 64, mask alignment steps in the photolithography process are performed with reference to the device isolation oxide film 52 having been already formed.
After that, an N-type impurity such as arsenic and like impurities is injected into the active region in self-align manner with the use of the first floating gate 54 and the second floating gate 55 both serving as masks. Then, as shown in FIG. 33A, the first floating gate 54 and the second floating gate 55 thus formed are subjected to a heat treatment, so that the N-type drain regions 56, 57 and the N-type source region 58 are formed and used as the buried diffusion layers. When an oxidation process is conducted after completion of the above heat treatment, oxidation of a surface of each of these diffusion layers 56, 57 and 58 which are highly doped with the N-type impurity is enhanced. As a result, as shown in FIG. 33B, an oxide film 66 larger in film thickness than the gate oxide film 53 is formed. Consequently, all the drain region 56, 57 and the source region 58 are covered by the oxide film 66, and therefore buried in the semiconductor substrate 51 to serve as the buried diffusion layers.
Next, as shown in FIG. 33B, by using the CVD process, a floating gate covering insulation film 60 constructed of the ONO (i.e., Oxide-Nitride-Oxide) laminated film is formed to cover both the first floating gate 54 and the second floating gate 55. After that, by using the CVD process, a second conductive layer 67 made of polysilicon is formed on the entire surface of the semiconductor substrate 51, and then patterned to form the control gate 61, so that the nonvolatile semiconductor memory device of the conventional type shown in FIGS. 30 and 31 is produced.
However, the conventional method for manufacturing the nonvolatile semiconductor memory device disclosed in the above-mentioned Japanese Patent Laid-Open No. Hei 6-283721 has the disadvantage that: in forming the floating gates through the patterning operation of the conductive layers, some misalignment occurs with respect to the device isolation oxide film which provides a reference position during the photolithography process. Due to the presence of such misalignment, among the buried diffusion layers disposed adjacent to the outer end portions of the floating gates, a left-hand one differs in width from a right-hand one.
In other words, in the conventional method of manufacturing the nonvolatile semiconductor device shown in FIGS. 32A, 32B, 32C, 33A and 33B, when the first floating gate 54 and the second floating gate 55 are formed by patterning the first conductive layer 64, it is necessary to previously form the resist film 65 on the first conductive layer 64, wherein the resist film 65 serves as the mask. Consequently, a mask alignment operation of this mask on the semiconductor substrate 51 is conducted by using the position of the device isolation oxide film 52 as a reference position of this mask.
However, such mask alignment operation inevitably includes some mechanical misalignment occurring in an optical aligner, and is therefore inadequate in processing accuracy to a today""s photolithography technology requiring a very fine processing. In FIG. 32C, due to the presence of the above-mentioned mechanical misalignment occurring in the optical aligner, the resist film 65 is slightly deviated in position to the right or to the left from its designed position. As a result of such deviation in position of the resist film 65, any of the drain regions 56, 57 and the source region 58 varies in width. In other words, these regions 56, 57 and 58 are not equal in width to each other.
Consequently, each of the buried diffusion layers used as the bit lines disposed adjacent to the outer end portions of both the first floating gate 54 and the second floating gate 55 varies in width. Variations in width of these buried layers result in corresponding variations in electric resistance of the buried diffusion layers. Due to the above fact, the conventional nonvolatile semiconductor memory device varies in read current, which often results in errors in reading data. Particularly, in the conventional nonvolatile semiconductor memory device comprising a plurality of memory cells for storing data having multi values, i.e., more particularly, in the conventional nonvolatile semiconductor memory device in which the read currents the number of which is more than three are judged and retrieved as data, even a slight variation in the read current often results in errors in reading data.
On the other hand, FIG. 34 shows another conventional nonvolatile semiconductor memory device in which the buried diffusion layers are disposed adjacent to opposite end portions of a single floating gate. As is clear from FIG. 34, the above-mentioned misalignment also affects in performance such another conventional nonvolatile semiconductor memory device.
In view of the above, it is an object of the present invention to provide a method of manufacturing a semiconductor, a nonvolatile semiconductor memory device and a method of manufacturing the same, wherein the semiconductor and the nonvolatile semiconductor memory device are free from variations in width of a buried diffusion layer disposed adjacent to each of outer end portions of floating gates, which variations in width of the buried diffusion layer are caused by mechanical misalignment occurring in the optical aligner.
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device provided with a gate electrode and a diffusion layer disposed adjacent to each of opposite end portions of the gate electrode, the method comprising the steps of:
forming a conductive layer on a semiconductor substrate through an insulation film;
patterning the conductive layer to form the gate electrode together with a shielding electrode, wherein the shielding electrode is disposed adjacent to each of opposite end portions of the gate electrode to extend in parallel with the gate electrode;
injecting an impurity into the semiconductor substrate in a self-align manner with the use of both the gate electrode and the shielding electrode as masks to form the diffusion layer covering adjacent ones of transistor cells; and
insulating the gate electrode in each of the transistor cells.
According to a second aspect of the present invention, there is provided a nonvolatile semiconductor memory device provided with a plurality of integrated nonvolatile semiconductor memory cells each comprising: a lower floating gate; a control gate formed on the lower floating gate through an insulation film; a diffusion layer disposed adjacent to each of opposite end portions of the lower floating gate, the improvement wherein:
a device isolation shielding electrode is formed outside the diffusion layer disposed adjacent to the opposite end portions of the lower floating gate; and,
the device isolation shielding electrode extends in parallel with the lower floating gate to cover adjacent ones of the nonvolatile semiconductor memory cells.
In the foregoing second aspect, a preferable mode is one wherein an upper floating gate larger in area size than the lower floating gate is formed on the lower floating gate.
Also, a preferable mode is one wherein the lower floating gate is constructed of a first floating gate and a second floating gate extending in parallel with the first floating gate; and,
a common diffusion layer disposed adjacent to an area between the first and the second floating gate so as to be common to both the first and the second floating gate.
Also, a preferable mode is one wherein the lower floating gate is made of a predetermined conductive material, of which the device isolation shielding electrode is also made. In the above nonvolatile semiconductor memory device, preferably, the predetermined conductive material is constructed of polysilicon.
Also, a preferable mode is one wherein the diffusion layer covers adjacent ones of the nonvolatile semiconductor memory cells.
Also, a preferable mode is one wherein the lower floating gate is insulated in each of the nonvolatile semiconductor memory cells.
Also, a preferable mode is one wherein the diffusion layer is constructed of a source region or a drain region of each of the nonvolatile semiconductor memory cells.
Also, a preferable mode is one wherein the device isolation shielding electrode is held at ground potential or at a source potential.
Furthermore, a preferable mode is one wherein the diffusion layer serves as a bit line.
According to a third aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device provided with a plurality of integrated nonvolatile semiconductor memory cells each comprising: a lower floating gate; a control gate formed on the lower floating gate through an insulation film; a diffusion layer disposed adjacent to each of opposite end portions of the lower floating gate, the method comprising the steps of:
forming a first conductive layer on a semiconductor substrate through an insulation film;
patterning the first conductive layer to form the lower floating gate together with a device isolation shielding electrode, wherein the shielding electrode is disposed adjacent to each of opposite end portions of the gate electrode to extend in parallel with the lower floating gate; and
injecting an impurity into the semiconductor substrate in a self-align manner with the use of both the lower floating gate and the device isolation shielding electrode as masks to form the diffusion layer.
In the foregoing third aspect, it is preferable that in the step of pattering the first conductive layer to form the lower floating gate together with the device isolation shielding electrode, a first floating gate and a second floating gate extending in parallel with the first floating gate are formed.
Also, it is preferable that in the step of injecting the impurity into the semiconductor substrate in a self-align manner with the use of both the lower floating gate and the device isolation shielding electrode as the masks to form the diffusion layer, the diffusion layer is so formed as to cover adjacent ones of the nonvolatile semiconductor memory cells.
Also, a preferable mode is one that wherein further comprises the steps of:
forming a floating gate covering insulation film for covering the lower floating gate, wherein the steps of forming the floating gate covering insulation film follows the step of injecting the impurity into the semiconductor substrate in the self-align manner with the use of both the lower floating gate and the device isolation shielding electrode as the masks to form the diffusion layer;
forming a second conductive layer for covering the floating gate covering insulation layer;
patterning the second conductive layer to form the control gate extending in a direction substantially perpendicular to a longitudinal direction of each of the lower floating gate and the device isolation shielding electrode; and
patterning the lower floating gate in a self-align manner with the use of the control gate as a mask to have only a portion of the lower floating gate immediately under the control gate remain.
Also, a preferable mode is one wherein the step of patterning the second conductive layer is performed by:
covering the second conductive layer with a second conductive layer covering insulation film;
patterning the second conductive layer covering insulation film to form a mask insulation film; and
using the mask insulation film as a mask.
Also, a preferable mode is one wherein the step of patterning the lower floating gate is performed by using both a resist film and the mask insulation film as masks in a self-align manner in a condition in which the device isolation shielding electrode is covered with the resist film.
Also, a preferable mode is one that wherein further comprises the step of forming a third conductive layer by:
covering the lower floating gate with a third conductive layer before the step of forming the floating gate covering insulation film is performed; and
patterning the third conductive layer in a manner such that the third conductive layer is larger in area size than the lower floating gate, so that an upper floating gate is formed.
Also, a preferable mode is one wherein each of the first, second and the third conductive layer is made of polysilicon.
With the above configurations, the lower floating gate is simultaneously formed together with the device isolation shielding electrodes disposed adjacent to the opposite end portions of the lower floating gate, wherein the device isolation shielding electrodes extend in parallel with the lower floating gate. Consequently, in the present invention, there is no fear that a left-hand and a right-hand regions both to be formed into the diffusion layers differ in width from each other even when some misalignment occurs as to the resist patterning mask which is used to form the lower floating gate with reference in position to the device isolation oxide film. This is because the lower floating gate is formed simultaneously with formation of the device isolation shielding electrodes disposed adjacent to the opposite end portions of the lower floating gate, wherein the device isolation shielding electrodes extend in parallel with the lower floating gate.
As a result, it is possible for the present invention to eliminate any variations in width of the buried diffusion layers disposed adjacent to the opposite end portions of the lower floating gate, wherein the variations in width are caused by misalignment occurring in the optical aligner.